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authorWilco Dijkstra <wilco.dijkstra@arm.com>2022-12-07 14:16:24 +0000
committerWilco Dijkstra <wilco.dijkstra@arm.com>2022-12-07 16:59:07 +0000
commit952c8a1dc6235dc49ab207a7f18f63d2bc97fbc9 (patch)
tree6a7e5252feda4b23ada0bbd879b9697a285e00b2 /gcc
parentMAINTAINERS: Add myself as Rust front-end maintainer (diff)
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AArch64: Fix assert in aarch64_move_imm [PR108006]HEADtrunkmaster
Ensure we only pass SI/DImode which fixes the assert. gcc/ PR target/108006 * config/aarch64/aarch64.cc (aarch64_expand_sve_const_vector): Fix call to aarch64_move_imm to use SI/DI.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/aarch64/aarch64.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 89bf0dff904..27a814d8621 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -6513,7 +6513,8 @@ aarch64_expand_sve_const_vector (rtx target, rtx src)
6513 /* If the integer can be moved into a general register by a 6513 /* If the integer can be moved into a general register by a
6514 single instruction, do that and duplicate the result. */ 6514 single instruction, do that and duplicate the result. */
6515 if (CONST_INT_P (elt_value) 6515 if (CONST_INT_P (elt_value)
6516 && aarch64_move_imm (INTVAL (elt_value), elt_mode)) 6516 && aarch64_move_imm (INTVAL (elt_value),
6517 encoded_bits <= 32 ? SImode : DImode))
6517 { 6518 {
6518 elt_value = force_reg (elt_mode, elt_value); 6519 elt_value = force_reg (elt_mode, elt_value);
6519 return expand_vector_broadcast (mode, elt_value); 6520 return expand_vector_broadcast (mode, elt_value);