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authorJohn Darrington <john@darrington.wattle.id.au>2018-11-20 18:50:30 +0100
committerJohn Darrington <john@darrington.wattle.id.au>2018-11-21 21:34:47 +0100
commit27f42a4ddb28514fde3d01083120674fc8c0c107 (patch)
tree3e064190c801dd9e278edcdfa81481133f620968
parentS12Z: Add alias instructions BHS and BLO. (diff)
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S12Z opcodes: Fix bug disassembling certain shift instructions.
Shift and rotate instructions when the number of bit positions was an immediate value greater than 1 were incorrectly disassembled. This change fixes that problem and extends the test to check for it. gas/ChangeLog: testsuite/gas/s12z/shift.s: Add new test case. testsuite/gas/s12z/shift.d: Add expected result. opcodes/ChangeLog: s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case if the postbyte matches the appropriate pattern.
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/testsuite/gas/s12z/shift.d4
-rw-r--r--gas/testsuite/gas/s12z/shift.s2
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/s12z-dis.c44
5 files changed, 40 insertions, 20 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c1d207d..1c99079 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
12018-11-21 John Darrington <john@darrington.wattle.id.au> 12018-11-21 John Darrington <john@darrington.wattle.id.au>
2 2
3 * testsuite/gas/s12z/shift.s: Add new test case.
4 * testsuite/gas/s12z/shift.d: Add expected result.
5
62018-11-21 John Darrington <john@darrington.wattle.id.au>
7
3 * config/tc-s12z.c (opcodes): bhs, blo: New members. 8 * config/tc-s12z.c (opcodes): bhs, blo: New members.
4 * testsuite/gas/s12z/bra.d: Add tests for aliases. 9 * testsuite/gas/s12z/bra.d: Add tests for aliases.
5 * testsuite/gas/s12z/bra.s: Add tests for aliases. 10 * testsuite/gas/s12z/bra.s: Add tests for aliases.
diff --git a/gas/testsuite/gas/s12z/shift.d b/gas/testsuite/gas/s12z/shift.d
index c3244c4..f4747c9 100644
--- a/gas/testsuite/gas/s12z/shift.d
+++ b/gas/testsuite/gas/s12z/shift.d
@@ -1,5 +1,5 @@
1#objdump: -d 1#objdump: -d
2#name: 2#name: Tests for shift and rotate instructions
3#source: shift.s 3#source: shift.s
4 4
5 5
@@ -20,3 +20,5 @@ Disassembly of section .text:
20 17: 10 3e 8e lsr.p \(d6,x\), #2 20 17: 10 3e 8e lsr.p \(d6,x\), #2
21 1a: 10 f4 bf asl d7, #1 21 1a: 10 f4 bf asl d7, #1
22 1d: 10 bc bd asr d1, #2 22 1d: 10 bc bd asr d1, #2
23 20: 16 de 78 asl d6, d6, #17
24 23: 16 d6 78 asl d6, d6, #16
diff --git a/gas/testsuite/gas/s12z/shift.s b/gas/testsuite/gas/s12z/shift.s
index cb41f3c..bf39580 100644
--- a/gas/testsuite/gas/s12z/shift.s
+++ b/gas/testsuite/gas/s12z/shift.s
@@ -9,3 +9,5 @@
9 lsr.p (d6,x), #2 9 lsr.p (d6,x), #2
10 asl d7, #1 10 asl d7, #1
11 asr d1, #2 11 asr d1, #2
12 asl d6, d6, #17
13 asl d6, d6, #16
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bfdca28..d5c44b5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
12018-11-21 John Darrington <john@darrington.wattle.id.au>
2
3 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
4 if the postbyte matches the appropriate pattern.
5
12018-11-13 Francois H. Theron <francois.theron@netronome.com> 62018-11-13 Francois H. Theron <francois.theron@netronome.com>
2 7
3 * nfp-dis.c: Fix crc[] disassembly if operands are swapped. 8 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
diff --git a/opcodes/s12z-dis.c b/opcodes/s12z-dis.c
index ad39e05..719f172 100644
--- a/opcodes/s12z-dis.c
+++ b/opcodes/s12z-dis.c
@@ -2363,25 +2363,31 @@ print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
2363 break; 2363 break;
2364 2364
2365 case SB_REG_REG_N: 2365 case SB_REG_REG_N:
2366 if (sb & 0x08) 2366 {
2367 { 2367 uint8_t xb;
2368 operand_separator (info); 2368 read_memory (memaddr + 1, &xb, 1, info);
2369 if (byte & 0x10) 2369 /* This case is slightly unusual.
2370 { 2370 If XB matches the binary pattern 0111XXXX, then instead of
2371 uint8_t xb; 2371 interpreting this as a general OPR postbyte in the IMMe4 mode,
2372 read_memory (memaddr + 1, &xb, 1, info); 2372 the XB byte is interpreted in s special way. */
2373 int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1); 2373 if ((xb & 0xF0) == 0x70)
2374 (*info->fprintf_func) (info->stream, "#%d", shift); 2374 {
2375 } 2375 operand_separator (info);
2376 else 2376 if (byte & 0x10)
2377 { 2377 {
2378 (*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__); 2378 int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
2379 } 2379 (*info->fprintf_func) (info->stream, "#%d", shift);
2380 } 2380 }
2381 else 2381 else
2382 { 2382 {
2383 opr_decode (memaddr + 1, info); 2383 (*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
2384 } 2384 }
2385 }
2386 else
2387 {
2388 opr_decode (memaddr + 1, info);
2389 }
2390 }
2385 break; 2391 break;
2386 case SB_REG_OPR_OPR: 2392 case SB_REG_OPR_OPR:
2387 { 2393 {