summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCarl Love <carll@us.ibm.com>2017-10-03 12:03:22 -0500
committerCarl Love <carll@us.ibm.com>2017-10-03 12:03:22 -0500
commit7fce2c5269f82a7d063c87335a25de84fc9acc64 (patch)
tree298abc25b28b467653662b26381c370b020b8008
parentmips32: add BE-exp files for several tests (diff)
downloadvalgrind-7fce2c5269f82a7d063c87335a25de84fc9acc64.tar.gz
valgrind-7fce2c5269f82a7d063c87335a25de84fc9acc64.tar.bz2
valgrind-7fce2c5269f82a7d063c87335a25de84fc9acc64.tar.xz
PPC64, Add support for the Data Stream Control Register (DSCR)
-rw-r--r--NEWS1
-rw-r--r--VEX/priv/guest_ppc_helpers.c1
-rw-r--r--VEX/priv/guest_ppc_toIR.c18
-rw-r--r--VEX/pub/libvex_guest_ppc32.h2
-rw-r--r--VEX/pub/libvex_guest_ppc64.h7
-rw-r--r--memcheck/mc_machine.c1
-rw-r--r--memcheck/mc_main.c2
7 files changed, 27 insertions, 5 deletions
diff --git a/NEWS b/NEWS
index 2dfcf32..ca61811 100644
--- a/NEWS
+++ b/NEWS
@@ -58,6 +58,7 @@ where XXXXXX is the bug number as listed below.
58384526 reduce number of spill instructions generated by VEX register allocator v3 58384526 reduce number of spill instructions generated by VEX register allocator v3
59384584 Callee saved registers listed first for AMD64, X86, and PPC architectures 59384584 Callee saved registers listed first for AMD64, X86, and PPC architectures
60n-i-bz Fix missing workq_ops operations (macOS) 60n-i-bz Fix missing workq_ops operations (macOS)
61385182 PPC64 is missing support for the DSCR
61 62
62Release 3.13.0 (15 June 2017) 63Release 3.13.0 (15 June 2017)
63~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 64~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 8230d65..34adf62 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
921 vex_state->guest_TEXASR = 0; 921 vex_state->guest_TEXASR = 0;
922 vex_state->guest_PPR = 0x4ULL << 50; // medium priority 922 vex_state->guest_PPR = 0x4ULL << 50; // medium priority
923 vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with 923 vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
924 vex_state->guest_DSCR = 0;
924} 925}
925 926
926 927
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index a8d4926..2467f70 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False;
296#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR) 296#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
297#define OFFB_PPR offsetofPPCGuestState(guest_PPR) 297#define OFFB_PPR offsetofPPCGuestState(guest_PPR)
298#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB) 298#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB)
299#define OFFB_DSCR offsetofPPCGuestState(guest_DSCR)
299 300
300 301
301/*------------------------------------------------------------*/ 302/*------------------------------------------------------------*/
@@ -459,6 +460,7 @@ typedef enum {
459 * automatically decrement. Could be added later if 460 * automatically decrement. Could be added later if
460 * needed. 461 * needed.
461 */ 462 */
463 PPC_GST_DSCR, // Data Stream Control Register
462 PPC_GST_MAX 464 PPC_GST_MAX
463} PPC_GST; 465} PPC_GST;
464 466
@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
3068 case PPC_GST_PSPB: 3070 case PPC_GST_PSPB:
3069 return IRExpr_Get( OFFB_PSPB, ty ); 3071 return IRExpr_Get( OFFB_PSPB, ty );
3070 3072
3073 case PPC_GST_DSCR:
3074 return IRExpr_Get( OFFB_DSCR, ty );
3075
3071 default: 3076 default:
3072 vex_printf("getGST(ppc): reg = %u", reg); 3077 vex_printf("getGST(ppc): reg = %u", reg);
3073 vpanic("getGST(ppc)"); 3078 vpanic("getGST(ppc)");
@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src )
3344 mkU64( 0x1C000000000000) ) ) ); 3349 mkU64( 0x1C000000000000) ) ) );
3345 break; 3350 break;
3346 } 3351 }
3352 case PPC_GST_DSCR:
3353 vassert( ty_src == Ity_I64 );
3354 stmt( IRStmt_Put( OFFB_DSCR, src ) );
3355 break;
3356
3347 default: 3357 default:
3348 vex_printf("putGST(ppc): reg = %u", reg); 3358 vex_printf("putGST(ppc): reg = %u", reg);
3349 vpanic("putGST(ppc)"); 3359 vpanic("putGST(ppc)");
@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
9407 putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ), 9417 putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ),
9408 /* Signed */False) ); 9418 /* Signed */False) );
9409 break; 9419 break;
9420 case 0x3: // 131
9421 DIP("mfspr r%u (DSCR)\n", rD_addr);
9422 putIReg( rD_addr, getGST( PPC_GST_DSCR) );
9423 break;
9410 case 0x8: 9424 case 0x8:
9411 DIP("mflr r%u\n", rD_addr); 9425 DIP("mflr r%u\n", rD_addr);
9412 putIReg( rD_addr, getGST( PPC_GST_LR ) ); 9426 putIReg( rD_addr, getGST( PPC_GST_LR ) );
@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
9575 DIP("mtxer r%u\n", rS_addr); 9589 DIP("mtxer r%u\n", rS_addr);
9576 putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) ); 9590 putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) );
9577 break; 9591 break;
9592 case 0x3:
9593 DIP("mtspr r%u (DSCR)\n", rS_addr);
9594 putGST( PPC_GST_DSCR, mkexpr(rS) );
9595 break;
9578 case 0x8: 9596 case 0x8:
9579 DIP("mtlr r%u\n", rS_addr); 9597 DIP("mtlr r%u\n", rS_addr);
9580 putGST( PPC_GST_LR, mkexpr(rS) ); 9598 putGST( PPC_GST_LR, mkexpr(rS) );
diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index 816ef5a..bb48ac5 100644
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -252,8 +252,8 @@ typedef
252 /* 1388 */ ULong guest_PPR; // Program Priority register 252 /* 1388 */ ULong guest_PPR; // Program Priority register
253 /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper 253 /* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
254 /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register 254 /* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register
255 /* 1404 */ ULong guest_DSCR; // Data Stream Control register
255 /* Padding to make it have an 16-aligned size */ 256 /* Padding to make it have an 16-aligned size */
256 /* 1404 */ UInt padding2;
257 /* 1408 */ UInt padding3; 257 /* 1408 */ UInt padding3;
258 /* 1412 */ UInt padding4; 258 /* 1412 */ UInt padding4;
259 } 259 }
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 02c4020..8c01fa6 100644
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -292,11 +292,12 @@ typedef
292 /* 1686 */ ULong guest_PPR; // Program Priority register 292 /* 1686 */ ULong guest_PPR; // Program Priority register
293 /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper 293 /* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
294 /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register 294 /* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register
295 /* 1702 */ ULong guest_DSCR; // Data Stream Control register
295 296
296 /* Padding to make it have an 16-aligned size */ 297 /* Padding to make it have an 16-aligned size */
297 /* 1698 */ UInt padding1; 298 /* 1710 */ UInt padding1;
298 /* 1702 UInt padding2; */ 299 /* 1714 */ UInt padding2;
299 /* 1706 UInt padding3; */ 300 /* 1718 */ UInt padding3;
300 301
301 } 302 }
302 VexGuestPPC64State; 303 VexGuestPPC64State;
diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 3ff7c44..1d57e0c 100644
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
194 if (o == GOF(TFIAR) && sz == 8) return -1; 194 if (o == GOF(TFIAR) && sz == 8) return -1;
195 if (o == GOF(PPR) && sz == 8) return -1; 195 if (o == GOF(PPR) && sz == 8) return -1;
196 if (o == GOF(PSPB) && sz == 8) return -1; 196 if (o == GOF(PSPB) && sz == 8) return -1;
197 if (o == GOF(DSCR) && sz == 8) return -1;
197 198
198 // With ISA 2.06, the "Vector-Scalar Floating-point" category 199 // With ISA 2.06, the "Vector-Scalar Floating-point" category
199 // provides facilities to support vector and scalar binary floating- 200 // provides facilities to support vector and scalar binary floating-
diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index a9a565b..892e503 100644
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid,
4468static void mc_post_reg_write ( CorePart part, ThreadId tid, 4468static void mc_post_reg_write ( CorePart part, ThreadId tid,
4469 PtrdiffT offset, SizeT size) 4469 PtrdiffT offset, SizeT size)
4470{ 4470{
4471# define MAX_REG_WRITE_SIZE 1728 4471# define MAX_REG_WRITE_SIZE 1744
4472 UChar area[MAX_REG_WRITE_SIZE]; 4472 UChar area[MAX_REG_WRITE_SIZE];
4473 tl_assert(size <= MAX_REG_WRITE_SIZE); 4473 tl_assert(size <= MAX_REG_WRITE_SIZE);
4474 VG_(memset)(area, V_BITS8_DEFINED, size); 4474 VG_(memset)(area, V_BITS8_DEFINED, size);