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authorCarl Love <cel@us.ibm.com>2017-10-03 10:49:48 -0500
committerCarl Love <carll@us.ibm.com>2017-10-03 15:19:53 -0500
commitf0c4da68ca9e8c99f55965d8e074273a33ab916d (patch)
tree7995ca6d30cef3d262ddb0b0b36c7e57eb617e9f
parentPPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. (diff)
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PPC64, Fix bug in vperm instruction.
The ISA says: Let the source vector be the concatenation of the contents of VR[VRA] followed by the contents of VR[VRB]. For each integer value i from 0 to 15, do the following. Let index be the value specified by bits 3:7 of byte element i of VR[VRC]. So, the index value is 5-bits wide ([3:7]), not 4-bits wide.
-rw-r--r--VEX/priv/guest_ppc_toIR.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 1785959..97664c2 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -24047,12 +24047,12 @@ static Bool dis_av_permute ( UInt theInstr )
24047 IRTemp vC_andF = newTemp(Ity_V128); 24047 IRTemp vC_andF = newTemp(Ity_V128);
24048 DIP("vperm v%d,v%d,v%d,v%d\n", 24048 DIP("vperm v%d,v%d,v%d,v%d\n",
24049 vD_addr, vA_addr, vB_addr, vC_addr); 24049 vD_addr, vA_addr, vB_addr, vC_addr);
24050 /* Limit the Perm8x16 steering values to 0 .. 15 as that is what 24050 /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
24051 IR specifies, and also to hide irrelevant bits from 24051 IR specifies, and also to hide irrelevant bits from
24052 memcheck */ 24052 memcheck */
24053 assign( vC_andF, 24053 assign( vC_andF,
24054 binop(Iop_AndV128, mkexpr(vC), 24054 binop(Iop_AndV128, mkexpr(vC),
24055 unop(Iop_Dup8x16, mkU8(0xF))) ); 24055 unop(Iop_Dup8x16, mkU8(0x1F))) );
24056 assign( a_perm, 24056 assign( a_perm,
24057 binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); 24057 binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) );
24058 assign( b_perm, 24058 assign( b_perm,