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* Merge VEX_3_13_BRANCH into VALGRIND_3_13_BRANCHsvn/VALGRIND_3_13_0svn/VALGRIND_3_13_BRANCHIvo Raisr2017-08-14159-0/+633275
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| * Merge, from trunk, r3385 (Handle x86 CET prefixes (32 bit only)).Julian Seward2017-05-311-1/+51
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| | * Handle x86 CET prefixes (32 bit only). Pertains to #379525.Julian Seward2017-05-301-1/+51
| * | Create branches/VEX_3_13_BRANCH as a copy of trunk r3383.Julian Seward2017-05-240-0/+0
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| * Handle x86 CET prefixes (64 bit only). Fixes #379525.Julian Seward2017-05-241-5/+14
| * mips: implement missing case for Iop_Not64Petar Jovanovic2017-05-221-0/+13
| * mips: fix set_MIPS_rounding_mode()Petar Jovanovic2017-05-221-2/+2
| * mips32: add Iex_ITE implementation for floating point numbersPetar Jovanovic2017-05-221-12/+11
| * Allow "sub.w reg, sp, reg, lsl #N" for N in 0 .. 5 rather than N in 0 .. 3.Julian Seward2017-05-221-2/+2
| * Fix some warnings reported by PVS studio (see bug 379502)Philippe Waroquiers2017-05-203-3/+3
| * mips: fix a typo in logPetar Jovanovic2017-05-191-1/+1
| * Missing VEX commit for Valgrind SVN r16393.Ivo Raisr2017-05-181-3/+3
| * PPC64, ISA 3.0 fixesCarl Love2017-05-171-24/+31
| * Power PC ISA 3.0 fixes:Carl Love2017-05-161-28/+52
| * mips: rewrite parts of mips_dirtyhelper_rdhwrPetar Jovanovic2017-05-163-22/+30
| * Reduce the number of compiler warnings on MIPS platformsIvo Raisr2017-05-162-45/+43
| * arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable theJulian Seward2017-05-162-0/+4
| * Fix decoding failure in X86 VEX frontend.Ivo Raisr2017-05-151-2/+2
| * Implement PRFM (unscaled offset). Fixes #371503.Julian Seward2017-05-141-0/+20
| * Implement "mrs <reg>, cntfrq_el0". Fixes #368868.Julian Seward2017-05-143-0/+38
| * Bug 367543 - bt/btc/btr/bts x86/x86_64 instructions are poorly-handled wrt fl...Julian Seward2017-05-131-10/+23
| * Enable the PCMPxSTRx variant $0x10. Fixes #372188.Julian Seward2017-05-122-2/+2
| * Implement ADCX and ADOX instructions. Modified version of a patch fromJulian Seward2017-05-123-64/+231
| * Bug 371491 - handleAddrOverrides() is truncating the segment base address whe...Julian Seward2017-05-111-4/+4
| * Remove TileGX/Linux port.Ivo Raisr2017-05-0813-18149/+1
| * mips: improve support for RDHWR instructionPetar Jovanovic2017-05-083-41/+21
| * mips: reduce compile warningsPetar Jovanovic2017-05-051-5/+2
| * Update copyright end year to 2017 in preparation for 3.13 release.Ivo Raisr2017-05-0496-102/+102
| * PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,Carl Love2017-05-034-271/+650
| * mips: remove unnecessary codePetar Jovanovic2017-05-031-8/+4
| * mips: add missing assembler directive to ASM_VOLATILE_UNARY64Petar Jovanovic2017-04-251-0/+1
| * mips: remove unnecessary code from FCSR_fp32 dirty helperPetar Jovanovic2017-04-251-39/+0
| * mips: limit cvt.s.l instruction translation to fp_mode64Petar Jovanovic2017-04-251-5/+9
| * widen_z_16_to_64, widen_z_8_to_64: generate less stupid code.Julian Seward2017-04-241-8/+6
| * Bug 369459 - valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)Julian Seward2017-04-248-26/+339
| * fix early initialization of s390_host_hwcaps in LibVEX_FrontEndPetar Jovanovic2017-04-121-3/+5
| * mips: update code for Dis_Resteer for mode64Petar Jovanovic2017-04-111-1/+4
| * Mark VPMULHRSW ymm3/m256, ymm2, ymm1 as a "verbose instruction". ThisJulian Seward2017-04-111-0/+1
| * Initialize s390_host_hwcaps early in LibVEX_FrontEnd.Mark Wielaard2017-04-041-2/+3
| * mips64: sign-extend results from dirty helperPetar Jovanovic2017-04-032-43/+5
| * Split LibVEX_Translate into front- and back-end parts. Also, removes useJulian Seward2017-04-033-383/+509
| * x86 guest: switch descriptor table registers to ULong type so they will take upJulian Seward2017-04-032-2/+6
| * Add a mechanism for hinting to the core disassembler loop, that theJulian Seward2017-03-2911-7/+52
| * Implement the most important cases for amd64 direct-reload optimisation:Julian Seward2017-03-283-0/+74
| * Rewrite dis_FMA so it generates not-quite-so-terrible code. It's still terribleJulian Seward2017-03-271-119/+89
| * Use consistently chase1() in MSVC specific transformation hacks.Ivo Raisr2017-03-241-1/+1
| * Fix type of t_inc to correct IRTemp.Ivo Raisr2017-03-141-1/+1
| * The mask64 value, in file VEX/priv/guest_ppc_toIR.c is missing theCarl Love2017-03-131-1/+1
| * mips: emulate LL/SC w/ guest_LLaddr and guest_LLdataPetar Jovanovic2017-03-135-42/+147
| * PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd,Carl Love2017-03-101-5/+24